Recently, a static column mode capable of realizing a high speed read out operation with a reduced cycle time has been implemented in a dynamic random acess memory (DRAM). In this static column mode initial data is accessed at the usual operation timing, and thereafter a high speed access is realized by activating a column address system as in the case of static random access memory (SRAM). The column address system is constituted by a static circuit which is not activated prior to operation. The I/O bit line is pulled up to a predetermined DC voltage by an I/O load, but does not fully swing between source voltage Vcc and ground at the read out operation. In this arrangement, however, there is a disadvantage in that a DC current always flows from the I/O load to the selected bit line. To overcome this disadvantage, a pulse signal operation system in which the selected column decoder is activated only in a predetermined time period during a read out operation is implemented.
FIG. 4 shows a typical column decoder section of such a pulse signal operation system circuit. In FIG. 4, reference numeral 51 designates an inverter, numerals 52, 53, and 54 designate NAND gates, numerals 55, 56, 57, and 58 designate P channel MOS transistors, and numerals 59, 60, 61, 62, 63, 64, 65, and 66 designate N channel MOS transistors. Reference numeral 71 designates a selected column decoder, numeral 72 designates an I/O load, and numeral 73 designates a preamplifier to which the output of the I/O load 72 is connected through a latch. Reference numeral 74 designates a sense amplifier, reference characters BL, BL designate a bit line pair, and a characters I/O and I/O designate a complementary I/O line pairs.
Reference character CE designates a row system signal, which is activated after the sense operation. Reference character W designates a write in system signal, and reference character ATD designates a pulse signal that is the output of an address transition detection circuit. This pulse signal ATD corresponds to a column decoder activating signal. Furthermore, reference character PAE designates a preamplifier activating signal, which is a signal having the same timing characteristics as the ATD signal. Reference character So designates an activating signal for the N channel sense amplifier 74a, and reference character So designates an activating signal for the P channel sense amplifier 74b. Reference character Ai designates a column address, and reference character Yj designates an output of the column decoder.
FIG. 5 shows an address transition detection circuit of a prior art semiconductor memory device which is designed to detect the transition of an address and to output a pulse signal upon that detection. In FIG. 5, reference numerals 1 to 11 designate inverters, reference numerals 12 to 15 designate NOR gates, and reference character Ai designates a column address. The inverters 1 to 4 and 6 to 9 respectively constitute delay stages.
The operating principle of the device of FIG. 5 will be described with reference to FIG. 6 which shows waveforms at the respective terminals of FIG. 5.
When the column address Ai is at low level, the terminal le is at high level because the terminals 1a and 1b are at low level, and the terminal 1f is at low level because the terminals 1c and 1d are at high level, and the output ATi is at low level. When the column address Ai changes to high level, the terminal 1a becomes high level, and the terminal 1e becomes low level. Therefore, the output ATi becomes high level. Thereafter, terminals 1c and 1d become low level, and the terminal 1f becomes high level. Therefore the output ATi becomes low level, and a pulse signal is output as the output ATi. The pulse signal ATi is also output when the column address Ai changes from high level to low level but in reverse to the above-described transition. The width of the high level of the output ATi can be adjusted depending on the number of delay stages. This width is established to be longer than that required for the output to be latched to the preamplifier (about 20 ns). The respective outputs ATi are input to the NOR gate 15, and a monopulse signal ATD is generated.
The operating principle of the circuit of FIG. 4 will be described with reference to FIG. 7.
Now suppose that the voltages of the bit line pair BL and BL are fixed to Vcc, the source voltage, and ground, respectively, after the sensing operation is completed and during a read out operation.
When the column address signal Ai makes a transition, the transition is detected and the ATD and ATD signal become high level and low level, respectively. Because the signals W and CE are both at high levels, the terminal 5b of FIG. 4 becomes high level. At the same time, the column decoder 71 is selected and the terminal 5a becomes low level. Thus, the output of the column decoder Yj becomes high level, and the data of bit line pair BL and BL flow into the I/O line pair I/O and I/O. Thereafter, the preamplifier activating signal PAE becomes high level synchronized with the ATD signal, and the data of the I/O line pair is latched in to the preamplifier. Thereafter, when the ATD signal is restored to high level, Yj becomes low level, the I/O line pair and the bit line pair are cut off from each other, and no DC current flows through the I/O load.
In the prior art semiconductor memory device with such a construction, there is a disadvantage in that the read out operation cannot take place when the same address is changed again during a time period shorter than the delay time of the delay stage of the address transition detection circuit.
The mechanism of this disadvantage will be described in detail.
In FIGS. 5 and 6, when the address Ai changes as shown by broken lines in FIGS. 5 and 6, the terminal 1a becomes low level, and the terminal 1e becomes high level. Therefore, the output ATi becomes low level. When the terminal 1b becomes high level, the terminal 1e becomes low level and the output ATi becomes high level. Thereafter the terminal 1b becomes low level and the terminal 1e becomes high level, again making the output ATi low level. After all, the width of the effective high level of the ATi is shortened from tw to tw'.
The operation waveforms of the respective portions when the signal ATi makes such a change are shown by broken lines in FIG. 7.
In the prior art semiconductor memory device of such a construction, when the address Ai is changed again during a short time period, the efficient width of the ATi is reduced. Therefore the pulse width of the preamplifier activating signal PAE, which has the same timing as the ATD signal, becomes narrower, thereby resulting in a disadvantage that data cannot be read out.